What Sony is doing with their own chip designs and fabs is not an issue. The question is whether or not IBM will be able to deliver. Sony, Nintendo and Microsoft all have their eggs in IBM’s basket for fabrication on the next-generation consoles.
I guess I don’t know much about consoles, but if the big three are really all based on the same chips, will there really be that big a difference between them? Does it all come down to the GPU and whatever else the manufacturer decides to throw in?
Well, in that case, if IBM is delayed, then no one gets a head start ;)
Microsoft and Nintendo are both relying on IBM for the processor and ATI for the GPU. Don’t know much about PS3 but I assume they’re using cell to do everything? As far as GPU is concerned the XBox2 and N5 teams at ATI are seperate. I suppose how well they perform depends on how much money each company wants to spend and how good the team that designs their chip is.
Actually, smaller metal traces does equal more resistance. But this plays a very trivial role in the amount of heat generated. Smaller lithographies mean more gates per area. More gates mean more switching. More switching means more current consumed and more current always means more heat. Not to mention that smaller geometry usually allows faster switching so you can clock the thing faster and as you might guess faster clock speed just multiplies the switching/current and heat.
As far as the industry’s technology not meeting predictions, I believe it’s simply money. We are just emerging from a depression and one of the worst tech busts in history. The research is incredibly expensive and even though the tech is possible/available its still cutting edge and hard for companies to justify spending huge sums of cash for new tooling.
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PS3 details are hard to nail down. The hardware development is a Sony-Toshiba-IBM troika.
Don’t worry about that coffee - got it myself.
Just to follow up on Greasy Pig and Linoleum’s comments, and why DaveC thinks smaller feature size means less heat…
Up until the past couple of years Dave would have been right, because a smaller feature size means that the chip can be supplied with a lower voltage. Supplying a higher voltage can damage the transistors if it gets high enough, so you actually get forced to use lower voltages. Since power = voltage * current, a lower voltage results in a lower power. So as chips needed 5V, and then 3.3V, and then 1.something volts, power went down.
If anyone wants to know about CMOS transistors in more detail, I can try and dredge it out of long term memory.
So if you look at that equation (P=VI) you see that changes in current will also change the power. What we’ve seen recently is that the increase in current drawn by the chip outweighs the drop in supply voltage.
As feature size goes down and die size goes up, you get chips with more and more transistors. In CMOS there’s supposed to be very little current running through the transistor when it’s in the logical 1 or 0 state, but it draws current when switching between the two states. This is why GreasyPig says more gates switching faster draws more current, and uses more power. The switching faster part is because smaller transistors take less time to be switched between states, so your clock frequency for your chip goes up when you move to a smaller feature size. These two factors mean that you have more area on the chip drawing current more frequently, and so your power consumption goes up in spite of the lower supply voltage.
The other problem, and probably the one that I’ve inferred to be giving Intel fits at 90nm from what I’ve read on the web, is leakage current. You’ll note above that I said in CMOS there’s ‘supposed’ to be very little current runnning through the transistor. The problem is that the low supply voltage makes it harder to put the transistor solidly into a 1 or 0 state, and so since it looks a little like it’s switching, it draws current. In addition to this problem, there’s another problem at the gate of the transistor. I can go into more detail, but basically the gate is used as the input value to the transistor. There’s a thin film between the input and the main body of transistor. As your feature size get smaller, this layer gets thinner, and I think right now it’s 7 or 8 atoms thick. This film is supposed to keep electrons from flowing through the gate, but since it’s so thin, some electrons filter through and so you have leakage current.
The IBM SOI patents Linoleum referred to are for new materials to use in the film that do a better job of preventing the electrons from slipping through. Intel is avoiding SOI in order to avoid patent issues, but it means they have to deal with higher leakage current, and so more power. I saw an article on the Inquirer giving some projected power draws for Intel’s upcoming chips and IBM’s upcoming Power chips, and while I take the Inquirer with a grain of salt, it looks like IBM’s process is much nicer in terms of power dissipation. There are other parts of the transistor that leak, but I ‘think’ these are the major sources of current.
Of course I’ve been a software guy for 4 years and haven’t even looked at circuit design in all that time, so I may not have the above exactly right, but the basics should be there.
Now outside of power issues, there are a lot of process issues involved in getting 65nm lithography working, including lenses, mask generation, resist development, and a whole host of other things that XPav’s brother at Applied Materials will know more about than me. IBM’s already made the jump to copper metal layers, SOI, 12-inch wafers, and potentially strained silicon along with AMD (which seems to have partnered up with IBM for process development) so they just need to get smaller feature sizes to get 65nm working. I think Intel is making more changes than just size for 65nm, but I don’t know for sure if this is the case. If they are, that might explain why IBM is more optimistic about 65nm.
Yeah, the last time I actually worked with a CMOS chip was about 10 years ago.
Hey awesome, he got that information from “a source!” DUDE. That’s like, IRON CLAD right there!
Yeah, its the Register, but their source basically claims that the whole "our chips is made with a 90nm process!’ is just another form of marketing hype.